JN517X Datasheet, PDF (36/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Table 5.
SPICLK
Polarity
(CPOL)
0
0
1
1
SPI-bus configurations
Mode Description
Phase
(CPHA)
0
0
SPICLK is low when idle - the first edge is positive. Valid data is
output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
1
1
SPICLK is low when idle – the first edge is positive. Valid data is
output on SPIMOSI every positive edge. SPIMISO is sampled
every negative edge.
0
2
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
1
3
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI every negative edge. SPIMISO is
sampled every positive edge.
If more than one SPISEL line is to be used in a system, they must be used in numerical
order starting from SPISEL0. A SPISEL line can be automatically de-asserted between
transactions if required, or it may stay asserted over a number of transactions. For
devices such as memories where a large amount of data can be received by the master
by continually providing SPICLK transitions, the ability for the select line to stay asserted
is an advantage since it keeps the slave enabled over the whole of the transfer.
A transaction commences with the SPI-bus being set to the correct configuration, and
then the slave device is selected. Upon commencement of transmission, (1 to 32 bits)
data is placed in the FIFO data buffer and clocked out, at the same time generating the
corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of
data bits is being received from the slave as it transmits. The data that is received during
this transmission can be read (1 to 32 bits). If the master simply needs to provide a
number of SPICLK transitions to allow data to be sent from a slave, it should perform
transmit using dummy data. An interrupt can be generated when the transaction has
completed or alternatively the interface can be polled.
If a slave device wishes to signal the JN517x indicating that it has data to provide, it may
be connected to one of the DIO pins that can be enabled as an interrupt.
Figure 25 shows a complex SPI-bus transfer, reading data from a Flash device that can
be achieved using the SPI-bus master interface. The slave select line must stay low for
many separate SPI-bus accesses, and therefore manual slave select mode must be used.
The required slave select can then be asserted (active low) at the start of the transfer. A
sequence of 8-bit and 32-bit transfers can be used to issue the command and address to
the Flash device and then to read data back. Finally, the slave select can be deselected to
end the transaction.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
36 of 100