JN517X Datasheet, PDF (71/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Table 23. I²C-bus interface
Symbol Parameter
Conditions
f_clk
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_SU;DAT
t_HD;DAT
t_r
clock frequency
SCL; DIO4; pin 21
hold time (repeated)
START condition
LOW period of the
SCL clock
HIGH period of the
SCL clock
set-up time for a
repeated START
condition
data set-up time
data setup time SDA
data hold time
data hold time SDA
rise time
rise time SDA and SCL
t_f
fall time
fall time SDA and SCL
t_SU;STO
t_BUF
t_w(spike)
C_b
V_nL
V_nH
set-up time for STOP
condition
bus free time
between a STOP
and START
condition
spike pulse width
pulse width of spikes that will be
suppressed by input filters
capacitive load for
each bus line
noise margin at the
LOW level
noise margin at the LOW level for
each connected device (including
hysteresis)
noise margin at the
HIGH level
noise margin at the HIGH level for
each connected device (including
hysteresis)
Standard mode Fast mode
Min Max Min Max
0
100
0
400
[1] ₄
-
0.6
-
Unit
kHz
s
4.7
-
1.3
-
s
4
-
0.6
-
s
4.7
-
0.6
-
s
0.25 -
0.1
-
s
0^[2]
-
0^[2]
-
s
[3] _-
1000 20 + 0.1 300
ns
Cb
[3] _-
300
20 + 0.1 300
ns
Cb
4
-
0.6
-
s
4.7
-
1.3
-
s
-
60
-
60
ns
-
400
-
400
pF
0.1V_DD -
0.1V_DD -
V
0.2V_DD -
0.2V_DD -
V
[1] After this period, the first clock pulse is generated.
[2] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the CLK signal) to bridge
the undefined region of the falling edge of CLK.
[3] Following the I²C-bus specifications.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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