JN517X Datasheet, PDF (54/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
As soon as the slave sees a start condition on the bus, it will read the first byte (if 7-bit
slave address mode selected) or the first 2 bytes (if 10-bit slave address mode selected).
If the address received matches the address programmed into the slave by the user, it will
acknowledge the slave address, and enter respectively the Receiver or the Transmitter
mode, according to the slave address first byte LSB, respectively 0 or 1.
9.14.4.1 Slave receiver
All the received bytes are stored in the RX_FIFO and all bytes are acknowledged. The
slave cannot generate a NAck.
Remark: the generation of the acknowledge is automatic and no extra programming is
required.
If the RX_FIFO happens to be full (interrupt RX_FIFO_FULL) in the middle of a
transaction, the slave will automatically stretch the clock after the acknowledge of the last
byte stored, until some room is made in the RX_FIFO as shown in Figure 39.
7
SCL
RX_FIFO full:
Slave stretches
the clock
8
Ack
One or several bytes
have been fetched from
the RX_FIFO
1
2
SDA
Acknowledge
by Slave
RFF
interrupt out.
Master transmits again
aaa-015459
Fig 39. Slave receiver: RX_FIFO in middle of a transaction
The transaction is aborted only when a STOP or a RESTART is detected on the bus.
After the slave has been addressed in receiver mode, the RX_FIFO must be emptied
before the device is addressed again after a STOP or RESTART. This will be notified
externally via interrupt SRSD (Int_Status register bit 4), set when the slave receiver sees a
STOP or a RESTART on the bus. The RX_FIFO is then automatically blocked (I2C_Status
register bit 10 set) and must be emptied (read), before clearing the interrupt. Only then
can the slave be involved in a new transfer. If the slave is addressed again in receiver
mode and the RX_FIFO is not empty, the slave will stretch the clock after acknowledging
its address, until the RX_FIFO is completely emptied. This mechanism is present to
prevent multiple messages from being entered into the RX_FIFO, since the slave cannot
differentiate 2 distinct messages - START and STOP information is not stored.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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