JN517X Datasheet, PDF (69/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
14.3.2 SPI-bus master timing
SPISELx⁽¹⁾
SPICLK
(mode = 0, 1)
SPICLK
(mode = 2, 3)
SPIMISO
(mode = 0, 2)
SPIMISO
(mode = 1, 3)
SPIMOSI
(mode = 1, 3)
SPIMOSI
(mode = 0, 2)
t_su(S)
T_clk
t_su(D)
t_d(Q)
t_h(D)
t_h(D)
t_su(D)
t_d(Q)
(1) With x = 0, 1 or 2.
Fig 48. SPI-bus master timing
Table 21.
Symbol
T_clk
t_su(D)
SPI-bus master timing
Parameter
clock period
data input set-up time
t_h(D)
t_d(Q)
t_su(S)
t_h(S)
data input hold time
data output delay time
chip select set-up time
chip select hold time
Conditions
for SPI-bus clock on pin 23 DO0
3.3 V
2.8 V
2.0 V
for SPI-bus clock on pin 36 DIO11
3.3 V
2.8 V
2.0 V
on SPIMOSI
SPICLK = 16 MHz
SPICLK < 16 MHz; mode = 0 or 2
SPICLK < 16 MHz; mode = 1 or 3
t_h(S)
aaa-017275
Min Typ
62.5 -
Max Unit
-
ns
16.7 -
-
ns
18.2 -
-
ns
21
-
-
ns
20.2 -
23.3 -
25.3 -
0
-
-
-
60
-
30
-
0
-
60
-
-
ns
-
ns
-
ns
-
ns
15
ns
-
ns
-
ns
-
ns
-
ns
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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