JN517X Datasheet, PDF (51/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Regardless of the direction of the communication in master mode the first thing that must
be done is to set the I²C-bus clock frequency, by programming both the
Clock_Divisor_High and Clock_Divisor_Low registers.
Then the programming depends on the function required for the device:
9.14.3.1 Master transmitter
1. The user has to write the TX_FIFO register with a slave address byte (with the LSB
set to 0 = write operation) and a start command bit, so that an I²C-bus transfer can be
initiated. The data bytes to be sent must then be loaded into the TX_FIFO register
(start and stop commands bits should be cleared to ‘0’). The matching slave device
will acknowledge the slave address and then each data byte so that the transaction
can continue.
2. If the TX_FIFO is empty, the master will automatically stretch the clock of the previous
byte (after acknowledge) until a new byte is written to the TX_FIFO as can be seen in
Figure 36. This stretching after acknowledge is the case for the address + R/W byte
(first) as well as for all data bytes that follow.
7
SCL
TX_FIFO empty:
Master stretches
the clock
8
Ack
One or several bytes
have been written to
TX_FIFO
1
2
JN517X
Product data sheet
SDA
Acknowledge
by Slave
MTDR
interrupt out.
Master transmits again
aaa-015456
Fig 36. TX_FIFO in the middle of a transaction
3. With the LAST data byte to be sent the user must set the stop bit to generate a STOP
condition and the slave should acknowledge the byte. For a RESTART to be issued
both start and stop bits should remain cleared at this point.
4. If a STOP has been produced, a new transaction can be initiated by jumping back to
step 1 of the master receiver or transmitter mode. Otherwise for the RESTART case,
the start bit has to be programmed together with the slave address of the next
transaction (start bit set).
The next action will be step 2 of the master receiver or Transmitter mode, depending on
the slave address direction bit. Table 10 is an example of master transmitter writing data
to TX_FIFO.
Table 10. I²C-bus TX_FIFO master transmitter writing data example
Instruction code
Description
0x148
master issues a START + slave address 24h (write operation)
0x025
data bytes 25h”, 13h will be sent to the slave” interrupt
0x013
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All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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