JN517X Datasheet, PDF (49/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
• Multi-master operation
• Software programmable clock frequency
• Supports Slave clock stretching
• Software programmable acknowledge bit
• Interrupt or polling driven data-transfers
Slave only:
• Read data flow control using clock stretching
• Read data preloaded or provided as required
The serial interface is accessed, depending upon the configuration, through DIO4 and
DIO5 which have true open-drain mode or DIO2 and DIO3. This is enabled under
software control. The following table details which DIO is used for the Serial Interface
depending upon the configuration.
Table 9.
Signal
SCL
SDA
2-wire serial interface I/O
DIO assignment
Standard pins
DIO4
DIO5
Alternative pins
DIO3
DIO2
9.14.1 Connecting devices
The clock and data lines, SCL and SDA, are alternate functions of DIO4 and DIO5
respectively. The serial interface function of these pins is selected when the interface is
enabled. They are both bidirectional lines, connected internally to the positive supply
voltage via weak (50 k) programmable pull-up resistors. However, it is recommended
that external 4.7 k pull-ups be used for reliable operation at high bus speeds, as shown
in Figure 34. When the bus is free, both lines are HIGH. The output stages of devices
connected to the bus must have an open-drain or open-collector in order to perform the
wired-AND function. The number of devices connected to the bus is solely dependent on
the bus capacitance limit of 400 pF.
DIO4 and DIO5 support fail-safe operation of the I²C-bus system bus, i.e., if the V_DD
supply is removed from the JN517x then rest of I²C-bus at system level is not affected.
However when alternate pins DIO2 and DIO3 are used as the I²C-bus interface the
fail-safe operation is not guaranteed as these DIOs do not have true open-drain output
stages.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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