JN517X Datasheet, PDF (52/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Table 10. I²C-bus TX_FIFO master transmitter writing data example …continued
Instruction code
Description
0x1DC
master issues a RESTART + slave address 6Eh (write)
0x001
data bytes 01h, AAh will be sent to the slave
0x2AA
master issues a STOP
9.14.3.2 Master receiver
1. The user has to write the TX_FIFO register with a slave address byte (with the LSB
set to 1 = read operation) and a start command bit, so that an I²C-bus transfer can be
initiated. The slave will acknowledge if it recognizes its address, and start transmitting
data.
2. For each data byte requested by the master, a dummy byte (i.e. the value of the data
byte can be anything from 0x00 to 0xFF) must be loaded into the TX_FIFO, so that
the master acknowledges the data bytes it receives. Please note that the
acknowledge bit is generated automatically; no specific programming is required for it.
The received (acknowledged) data bytes will be stored in the RX_FIFO (address
0x000), from where they can be fetched by the bus system interface. If the RX_FIFO
happens to be full (interrupt RX_FIFO_FULL) in the middle of a transaction, the
master will automatically stretch the clock before the acknowledge of the last byte that
is stored, until some room is made in the RX_FIFO, refer to Figure 37. The data is
actually written into the RX_FIFO on the 8^th clock cycle, so it can be read by software
even if the clock is currently stretched in the Ack cycle (9^th clock) due to
RX_FIFO_Full.
6
SCL
RX_FIFO full:
Master stretches
the clock
7
8
One or several bytes
have been fetched from
the RX_FIFO
Ack
1
2
JN517X
Product data sheet
SDA
RFF
interrupt out.
Acknowledge
by Master
Slave transmits again
aaa-015457
Fig 37. RX_FIFO full in the middle of a transaction
3. When the LAST data byte has to be received, the user must set the stop bit with the
last dummy byte to generate a STOP condition. In this case, the master will NOT
Acknowledge the byte, so that the slave releases the data line and the STOP can be
issued by the master
If the TX_FIFO is empty, the master will automatically stretch the clock. If the
TX_FIFO becomes empty, the clock will be stretched after the acknowledgement has
been sent. This behavior is identical to the master transmitter as shown in Figure 36.
However when the TX_FIFO is empty after sending a dummy byte (in order to receive
a byte from the slave) the clock will be stretched between the 8^th cycle and the Ack
cycle, until at least one new byte is written to the TX_FIFO. This is shown in
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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