JN517X Datasheet, PDF (50/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
JN517x
DIO4 ^SCL
I²C-bus
SDA
DIO5
V_DD
RP
RP
pull-up
resistors
D1_IN
CLK1_IN
D2_IN
CLK2_IN
D1_OUT
CLK1_OUT
D2_OUT
CLK2_OUT
Fig 34. Connection details
DEVICE 1
DEVICE 2
aaa-0121462
9.14.2 Clock stretching
Slave devices can use clock stretching to slow down the read transfer bit rate. After the
master has driven SCL low, the slave can drive SCL low for the required period and then
release it. If the slave’s SCL low period is greater than the master’s low period the
resulting SCL bus signal low period is stretched thus inserting wait states, see
Section 9.14.4 for further details.
clock held low
by slave
SCL
master SCL
SCL
slave SCL
SCL
Fig 35. Clock stretching
system SCL
aaa-015455
9.14.3 Master interface
When operating as a master, it provides the clock signal and a separately programmable
SCL low and high period to determine the clock rate and shape, allowing operation up to
400 kbit/s.Data transfer is controlled from the processor bus interface by populating the
TX FIFO or managing the RX FIFO, with the I²C-bus controller taking care of when start,
stop, read, write and acknowledge control should be generated. To use the master device
as a receiver, one just needs to fill the TX_FIFO with a start condition and a valid slave
address (LSB = 1: read operation), and then with as many dummy bytes (i.e. any byte) as
the number of bytes requested from the slave device. A ‘stop’ must always be issued
together with a dummy byte in the TX_FIFO to indicate the slave no longer needs to send
data. The data received on the master side is stored in the RX_FIFO.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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