JN517X Datasheet, PDF (43/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
1N4007
M
+10 V
TACHO
JN517x PWM1
IRF521
CLK/GATE
TIMER0 CAPTURE
PWM
1 pulse/rev
Fig 31. Closed loop PWM speed control using JN517x timers
aaa-021461
9.10.2 ARM cortex-M3 system tick timer
The JN517x has a system tick timer (SysTick) which is a part of the Cortex-M3. SysTick,
that provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a
flexible control mechanism. A system can use this counter in several different ways,
including:
• As an RTOS tick timer that fires at a programmable rate, for example 100 Hz, and
invokes a SysTick routine each time it fires
• As a high-speed alarm timer using the main processor clock
• As a variable-rate alarm or signal timer. The available duration range depends on the
reference clock used and the dynamic range of the counter
• As a simple counter. Software can use this to measure time to completion and time
used
For further details, refer to JN-UG-3118 Integrated Peripherals API User Guide
JN-UG-3118 on the Wireless Connectivity area of the NXP web site Ref. 2.
In the JN517x, this timer can be clocked from the CPU clock or from a 32 kHz clock. The
32 kHz source can be either high-speed RC oscillator or 32 MHz crystal clock, suitably
divided down. When the high-speed RC oscillator is used as the clock source, the SysTick
clock may not be accurate 32 kHz.
9.10.3 Wake-up timers
Two 41-bit wake-up timers are available in the JN517x driven from the 32 kHz internal
clock. They may run during sleep periods when most of the rest of the device is powered
down, to time sleep periods or other long period timings that may be required by the
application. The wake-up timers do not run during deep sleep and may optionally be
disabled in sleep mode through software control. When a wake-up timer expires, it
typically generates an interrupt; if the device is asleep then the interrupt may be used as
an event to end the sleep period. See Section 10 for further details on how they are used
during sleep periods. Features include:
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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