JN517X Datasheet, PDF (46/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
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JN517X
Product data sheet
The serial interfaces contain programmable fields that can be used to set number of data
bits (5, 6, 7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of
single or multiple stop bit (for 5-bit data, multiple is 1.5 stop bits; for 6 data bits or 7 data
bits or 8 data bits, multiple is 2 bits).
The baud rate is programmable up to 1 Mbits/s and standard 4.8 kbits/s, 9.6 kbits/s,
19.2 kbits/s, 38.4 kbits/s.
For applications requiring hardware flow control, UART0 provides two control signals:
Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an
external device to the UART that it is ready to receive data. RTS is an indication sent by
the UART to the external device that it is ready to receive data. RTS is controlled from
software activities, while the value of CTS can be read. Monitoring and control of CTS and
RTS are software activity, normally performed as part of interrupt processing. The signals
do not control parts of the UART hardware, but simply indicate to software the state of the
UART external interfaces. Alternatively, the automatic flow control mode can be used, in
which the hardware controls the value of the generated RTS (negated if the receive FIFO
fill level is greater than a programmable threshold of 8 bytes, 11 bytes, 13 bytes or 15
bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the receive FIFO and can also
write to the transmit FIFO, one byte at a time. The transmit and receive FIFOs can be
cleared and reset independently of each other. The status of the transmit FIFO can be
checked to see if it is empty and if there is a character being transmitted. The status of the
receive FIFO can also be checked, indicating if a condition such as parity error, framing
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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