JN517X Datasheet, PDF (15/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
9. Functional description
9.1 CPU
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-CODE bus,
and the D-CODE bus. The I-CODE and D-CODE core buses are faster than the system
bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch
(I-CODE) and one bus for data access (D-CODE). The use of 2 core buses allows for
simultaneous operations if concurrent operations target different devices.
The JN517x uses a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on the official ARM website.
To improve power consumption a number of power-saving modes are implemented in the
JN517x, described more fully in Section 10. One of these modes is the CPU doze mode;
under software control, the processor can be shut down and on receiving an interrupt it
will wake up to service the request. Additionally, it is possible under software control, to
set the speed of the CPU to 1 MHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz or 32 MHz. This
feature can be used to trade off processing power against current consumption.
9.2 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to 8 breakpoints and 4 watch
points.
9.3 Memory organization
This section describes the different memories found within the JN517x. The device
contains Flash, RAM, and EEPROM memory, the wireless transceiver and peripherals
registers all within the same linear address space.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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