JN517X Datasheet, PDF (37/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
SPISELx⁽¹⁾
SPICLK
SPIMOSI
SPIMISO
instruction transaction
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
Instruction (0x03)
24-bit address
23 22 21
MSB
3
2
1
0
read data bytes transaction(s) 1-N
SPISELx⁽¹⁾
0
1
2
3
4
5
6
7
8
9 10
SPICLK
8N-1
SPIMOSI
value unused by peripherals
SPIMISO
7
6
5
4
3
2
1
0
7
6
5
3
MSB
MSB
byte 1
byte 2
(1) With x = 0 or 1 or 2.
Fig 25. Example SPI-bus waveforms: reading from Flash device using mode 0
2
1
0
LSB
byte N
aaa-015449
9.9.2 SPI-bus slave
The SPI-bus slave interface allows high-speed synchronous data transfer between the
JN517x and a peripheral device. The JN517x operates as a slave on the SPI-bus and an
external device, connected to the SPI-bus operates as the master. The pins are different
from the SPI-bus master interface and are shown in the Table 6.
Table 6. SPI-bus slave I/O
Signal
SPISCLK
SPISMISO
SPISMOSI
SPISSEL
DIO assignment
Standard pins
DIO6
DO1
DIO11
DIO7
Alternative pins
DIO18
DIO17
DIO14
DIO15
The SPI-bus employs a simple shift-register data transfer scheme, with SPISSEL acting
as the active low select control. Data is clocked out of and into the active devices in a
first-in, first-out fashion allowing SPI-bus devices to transmit and receive data
simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the
clock signal SPISCLK generated by the external master.
The SPI-bus slave includes the following features:
• Full-duplex synchronous data transfer
• Supports external clock up to 8 MHz
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
37 of 100