JN517X Datasheet, PDF (48/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
9.12.2 UART application
The following example shows the UART0 connected to a 9-pin connector compatible with
a PC. As the JN517x device pins do not provide the RS232 line voltage, a level shifter is
used.
JN517x
TXD
CTS
UART0
RXD
RTS
RS232
LEVEL
SHIFTER
PC COM
port
1
5
6
9
pin
signal
1
CD
2
RD
3
TD
4
DTR
5
SG
6
DSR
7
RTS
8
CTS
9
RI
Fig 33. JN517x serial communication link
aaa-021456
9.13 JTAG test interface
The JN517x includes a JTAG interface for the purposes of software debugging when used
in conjunction with the LCPXpresso for NXP development environment.
For further details, refer to SDK Installation and User Guide JN-UG-3109 on the Wireless
Connectivity area of the NXP web site Ref. 2.
The JTAG interface does not support boundary scan testing. It is recommended that the
JN517x is not connected as part of the board scan chain.
9.14 2-wire serial interface (I²C-bus)
The JN517x includes industry standard I²C-bus 2-wire synchronous Serial Interface
operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method
of data exchange between devices. The system uses a serial data line (SDA) and a serial
clock line (SCL) to perform bidirectional data transfers and includes the following features:
Common to both master and slave:
• Compatible with both I²C-bus standard
• Support for 7 and 10-bit addressing modes
• Pulse suppression on signal inputs (60 ns guaranteed, 125 ns typical)
• True open-drain support on one set of DIOs
• Receive and transmit FIFO of depth of 8
• Bus monitor mode
• Fail-safe operation on DIO4 and DIO5
Master only:
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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