JN517X Datasheet, PDF (25/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
9.6.1 Interrupts sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Table 3 lists the interrupt sources for each peripheral function. Exception
numbers relate to where entries are stored in the exception vector table. Interrupt
numbers are used in some other contexts, such as software interrupts.
Table 3. Interrupt sources
Interrupt ID
Exception
number
0
16
1
17
2
18
3
19
4
20
5
21
6
22
7
23
8
24
9
25
10
26
11
27
12
28
13
29
14
30
15
31
16
32
17
33
18
34
19
35
Vector offset (h) Function
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x80
0x84
0x88
0x8C
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
system controller
MAC
AES codec
PHY controller
UART0
UART1
SPI-bus slave
SPI-bus master
I²C-bus master/slave
Timer0
Timer1
timer ADC
analog peripheral
watchdog interrupt
9.7 Wireless transceiver
The wireless transceiver comprises a 2.45 GHz radio, modem, a baseband processor, a
security coprocessor and PHY controller. These blocks, with protocol software provided
as a library, implement an IEEE802.15.4 standards-based wireless transceiver that
transmits and receives data OTA in the unlicensed 2.4 GHz band.
9.7.1 Radio
Figure 15 shows the single-ended radio architecture.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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