JN517X Datasheet, PDF (34/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
9.9 Serial Peripheral Interface-bus (SPI-bus)
9.9.1 SPI-bus master
The SPI-bus allows high-speed synchronous data transfer between the JN517x and
peripheral devices. The JN517x operates as a master on the SPI-bus and all other
devices connected to the SPI-bus are expected to be slave devices under the control of
the JN517x CPU. The SPI-bus includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Programmable bit rates (up to 16 Mbit/s)
• Programmable transaction size up to 32-bits
• Standard SPI-bus modes 0, 1, 2 and 3
• Manual or automatic slave select generation (up to 2 simultaneous slaves)
• Supports external data in little endian as well as big endian format
• Maskable “transaction complete” interrupt
• LSB First or MSB First Data Transfer
• Supports delayed read edges
16 MHz
CLOCK
DIVIDER
DATA BUFFER
SPI BUS
CYCLE
CONTROLLER
SPICLK
SPIMISO
SPIMOSI
DIV
CLOCK EDGE
data
SELECT
CHAR_LEN LSB
SELECT
LATCH
SPISEL0/1/2
aaa-015447
Fig 23. SPI-bus block diagram
The SPI-bus employs a simple shift-register data transfer scheme. Data is clocked out of
and into the active devices in a first-in, first-out fashion allowing SPI-bus devices to
transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out
data transfer is relative to the clock signal SPICLK generated by the JN517x.
The JN517x provides 3 slave selects, SPISEL0 to SPISEL2 to allow 2 simultaneous
SPI-bus peripherals on the bus. The Table 4 details which DIO is used for the SPISEL
signals depending upon the software configuration.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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