JN517X Datasheet, PDF (60/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
The CPU may perform other tasks while the data transfer and storage is being managed
independently by the DMA engine - the CPU only needs to configure the ADC sample
buffer mode and deal with the stored samples in the buffer when an interrupt occurs.
ADC sample buffer mode allows up to 8 analog inputs to be multiplexed in combination.
These inputs comprise 6 external inputs (ADC0 to 5, corresponding to IO pins), an
on-chip temperature sensor and an internal voltage monitor. Samples from all the selected
inputs will be produced on each timer trigger and stored in consecutive RAM locations.
9.16.2 Comparator
The JN517x contains one analog comparator, COMP1, that is designed to have true
rail-to-rail inputs and operate over the full voltage range of the analog supply V_DDA. The
hysteresis level can be set to a nominal value of 0 mV, 10 mV, 20 mV or 40 mV. The
source of the negative input signal for the comparator can be set to the internal voltage
reference, the negative external pin (COMP1M, which uses the same pin as DIO18) or the
positive external pin (COMP1P, on the same pin as DIO17). The source of the positive
input signal can be COMP1P or COMP1M. DIO17 and DIO18 cannot be used if the
external comparator inputs are needed. The comparator output is routed to an internal
register and can be polled, or can be used to generate interrupts. The comparator can be
disabled to reduce power consumption. DIO17 and DIO18 should be set to inputs with
pull-ups disabled, when using the comparator.
The comparator also has a low-power mode where the response time of the comparator is
slower than the normal mode, but the current required is greatly reduced. These figures
are specified in Section 14.3.8. It is the only mode that may be used during sleep, where a
transition of the comparator output will wake the device. The wake-up action and the
configuration for which edge of the comparator output is active are controlled through
software. In sleep mode, the negative input signal source must be configured to be driven
from the external pins.
9.16.3 Digital monitor for ADC output
The JN517x contains one digital monitor function at the output of the ADC. The digital
monitor can be configured to compare the ADC output against programmable upper
threshold (DC_UT) and lower threshold (DC_LT) and raise an interrupt on enabled trigger
conditions. The output of the monitor can also be brought out on DIO7. There are four
trigger conditions which can be selected:
• Less than: TRUE when ADC_VAL < DC_LT
• More than: TRUE when ADC_VAL > DC_UT
• Inside range: TRUE when DC_LT  ADC_VAL  DC_UT
• Outside range: TRUE when (ADC_VAL < DC_LT) OR (ADC_VAL > DC_UT)
10. Power management and sleep modes
10.1 Operating modes
After the main supply source is selected, 3 operating modes are provided in the JN517x
that enable the system power consumption to be controlled carefully to maximize battery
life.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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