JN517X Datasheet, PDF (47/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
error or break indication has occurred. It also shows if an overrun error has occurred
(receive buffer full and another character arrives) and if there is data held in the receive
FIFO.
UART0 and UART1 can both be configured to use standard or alternative DIO lines, as
shown in Table 8. Additionally, UART0 can be configured to be used in 2-wire mode
(where CTS0 and RTS0 are not configured), and UART1 can be configured in 1-wire
mode (where RXD1 is not configured). These freed up DIO pins can then be used for
other purposes.
Table 8. UART I/O
Signal
CTS0
RTS0
RXD0
TXD0
RXD1
TXD1
DIO assignment
Standard pins
DIO6
DIO11
DIO4
DIO5
DIO2
DIO3
Alternative pins
-
-
DIO10, DIO13
DIO9, DIO12
DIO6
DIO11
Remark: With the automatic flow control threshold set to 15, the hardware flow control
within the UART’s block negates RTS when the receive FIFO is about to become full. In
some instances, it has been observed that remote devices that are transmitting data do
not respond quickly enough to the de-asserted RTS and continue to transmit data. In
these instances, the data will be lost in a receive FIFO overflow
9.12.1 Interrupts
Interrupt generation can be controlled for the UART’s block and is divided into four
categories:
• Received Data Available: set when data in the RX FIFO queue reaches a particular
level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been
received for 4-character times.
• Transmit FIFO Empty: set when the last character from the TX FIFO is read and starts
to be transmitted
• Receiver Line Status: set when one of the following occurs
a. Parity Error - the character at the head of the receive FIFO has been received with
a parity error
b. Overrun Error - the RX FIFO is full and another character has been received at the
receiver shift register
c. Framing Error - the character at the head of the receive FIFO does not have a valid
stop bit
d. Break Interrupt – occurs when the RXD line has been held low for an entire
character
• Modem Status: generated when the CTS (Clear To Send) input control line changes.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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