JN517X Datasheet, PDF (40/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Table 7. Timer and PWM I/O …continued
Signal
DIO assignment
Standard pins
TIM1CAP
DIO6
TIM1OUT
DIO11
PWM1
DIO12
PWM2
DIO13
PWM3
DIO14
PWM4
DIO3
PWM5
DIO8
PWM6
DIO15
Alternative pins
DIO17
DIO18
-
-
-
-
-
-
The alternative pin locations can be configured separately for each counter/timer under
software control, without affecting the operation or location of the others. When operating
in timer mode, it is not necessary to use any of the DIO pins, allowing the standard DIO
functionality to be available to the application.
9.10.1.1 Pulse Width Modulation mode
Pulse Width Modulation (PWM) mode, as used by PWM timers 1, 2, 3, 4, 5 and 6 and
optionally by Timer0/Timer1, allows the user to specify an overall cycle time and pulse
length within the cycle. The pulse can be generated either as a single shot or as a train of
pulses with a repetition rate determined by the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the
values of two independent 17-bit registers (Fall and Rise). The counter-increments and its
output are compared to the 17-bit Rise and Fall registers. When the counter is equal to the
Rise register, the PWM output is set to high; when the counter reaches the Fall value, the
output returns to low. In continuous mode, when the counter reaches the Fall value, it will
reset and the cycle repeats. If either the cycle time or low periods are changed while in
continuous mode, the new values are not used until a full cycle has completed. The PWM
waveform is available on PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, TIM0OUT or
TIM1OUTwhen the output driver is enabled. The clock source used for pulse width
modulation could be 16 MHz or 32 MHz clock.
ULVH
Fig 27. PWM output timings
IDOO
DDD
9.10.1.2 Capture mode
The capture mode can be used to measure the time between transitions of a signal
applied to the capture input (TIM0CAP or TIM1CAP). When the capture is started, on the
next low-to-high transition of the captured signal, the count value is stored in the rise
register, and on the following high-to-low transition, the counter-value is stored in the fall
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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