JN517X Datasheet, PDF (32/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
the checksum at the end of the message to ensure that the data has been received
correctly. During reception, the modem determines the Link Quality, which is made
available at the end of the reception as part of the requirements of IEEE802.15.4.
9.7.3.3 Auto acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination
sending an acknowledge packet within a very short window after the transmitted frame
has been received. The JN517x baseband processor can automatically construct and
send the acknowledgement packet without processor intervention and hence avoid the
protocol software being involved in time-critical processing within the acknowledge
sequence. The JN517x baseband processor can also request an acknowledge for
packets being transmitted and handle the reception of acknowledged packets without
processor intervention.
9.7.3.4 Security
The transmission and reception of secured frames using the AES algorithm is handled by
the security coprocessor and the stack software. The application software must provide
the appropriate encrypt/decrypt keys for the transmission or reception. On transmission,
the key can be programmed at the same time as the rest of the frame data and set-up
information.
9.7.4 Security coprocessor
The security coprocessor is available to the application software to perform
encryption/decryption operations. A hardware implementation of the encryption engine
significantly speeds up the processing of the encrypted packets over a pure software
implementation. The AES library for the JN517x provides operations that utilize the
encryption engine in the device and allow the contents of memory buffers to be
transformed. Information such as the type of security operation to be performed and the
encrypt/decrypt key to be used must also be provided.
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Fig 22. Security coprocessor architecture
DDD
9.8 Digital Input Output
There are 18 Digital IO (DIO) pins which when used as general-purpose pins can be
configured as either an input or an output, with each having a selectable internal pull-up or
pull-down resistor. In addition, there are 2 Digital Output (DO) pins.
Most DIO pins are shared with the digital and analog peripherals of the device. When a
peripheral is enabled, it takes control over the device pins allocated to it. However, note
that most peripherals have two alternative pin allocations to alleviate clashes between
uses, and many peripherals can disable the use of specific pins if not required. Refer to
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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