JN517X Datasheet, PDF (70/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
14.3.3 SPI-bus slave timing
JN517x
IEEE802.15.4 Wireless Microcontroller
SPISSEL
t_su(S)
SPISCLK
t_su(D)
SPISMOSI
T_clk
t_h(D)
t_idle
t_h(S)
t_d(S-Q)
SPISMISO
Fig 49. SPI-bus slave timing
t_d(C-Q)
aaa-017276
Table 22. SPI-bus slave timing
Symbol Parameter
Conditions
T_clk
t_idle
t_su(D)
t_h(D)
t_d(C-Q)
clock period
idle time
data input set-up time
data input hold time
clock to data output
delay time
SPISCLK falling edge to SPISMISO output
delay time
t_d(S-Q)
chip select to data output SPISSEL falling edge to SPISMISO output
delay time
delay time
t_su(S)
chip select set-up time SPISSEL falling edge to SPISCLK rising edge
delay time
t_h(S)
chip select hold time
SPISCLK falling edge to SPISSEL rising edge
delay time
14.3.4 I²C-bus interface
Min Typ Max Unit
125 -
-
ns
125 -
-
ns
10
-
-
ns
10
-
-
ns
-
-
30
ns
-
-
30
ns
30
-
-
ns
30
-
-
ns
SDA
t_f
SCL
S
t_LOW
t_r
t_HD;STA t_HD;DAT
t_SU;DAT
t_HD;STA
t_f
t_HIGH
t_SU;STA
Sr
Fig 50. I²C-bus interface timing
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
t_w(spike)
t_r
t_BUF
t_SU;STO
P
S
aaa-015465
© NXP Semiconductors N.V. 2016. All rights reserved.
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