JN517X Datasheet, PDF (4/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
functionality can be developed rapidly by combining user-developed application software
with a protocol stack library.
4.2 CPU and memory
An ARM Cortex-M3 CPU allows software to be run on-chip, its processing power being
shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the
user application. The JN517x has a unified memory architecture, where code memory,
data memory, peripheral devices and IO ports are organized within the same linear
address space. The device contains 160 kB or 256 kB or 512 kB of Flash and 32 kB of
RAM and 4 kB EEPROM.
4.3 Peripherals
The following peripherals are available on chip:
• Master SPI-bus port with 2 simultaneous select outputs
• Slave SPI-bus port
• 2 UARTs: one capable of hardware flow control (4-wire, includes RTS/CTS) and the
other a 2-wire (RX/TX).
• 2 programmable timer/counters which support Pulse Width Modulation (PWM) and
capture/compare, plus 6 PWM timers which support PWM and Timer modes only.
• 2 programmable sleep timers and a system tick timer
• 2-wire serial interface (compatible with SMbus and I²C-bus) supporting master and
slave operation. Fail-safe open-drain IOs for I²C-bus.
• 18 digital IO lines (multiplexed with peripherals such as timers, SPI-bus and UARTs)
• 2 digital outputs (multiplexed with SPI-bus port)
• 10-bit, Analog-to-Digital Converter with 6 input channels. Autonomous multi-channel
sampling.
• Programmable analog comparator
• Digital comparator/monitor linked to ADC
• Internal temperature sensor and battery monitor
• 2 low-power pulse counters
• Random number generator
• Watchdog Timer and Supply Voltage Monitor (SVM)
• Debug support using serial-wire or 4-pin JTAG interface
• Debug trace port with up to 4 data lines.
• Transmit and receive antenna diversity with automatic receive switching based on
received energy detection
User applications access the peripherals using the Integrated Peripherals API. For further
details, refer to the JN517x Integrated Peripherals API User Guide, JN-UG-3118 on the
Wireless Connectivity area of the NXP web site Ref. 2. This allows applications to use a
tested and easily understood view of the peripherals allowing rapid system development.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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