JN517X Datasheet, PDF (41/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
register. The pulse width is the difference in counts in the two registers multiplied by the
period of the prescaled clock. Upon reading the capture registers, the counter is stopped.
The values in the high and low registers will be updated whenever there is a
corresponding transition on the capture input, and the value stored will be relative to when
the mode was started. Therefore, if multiple pulses are seen on capture input before the
counter is stopped only the last pulse width will be stored.
9
5
3
4
CLK
TIMxCAP⁽¹⁾
rise
t_r
t_r
t_f
t_f
capture mode enabled
x
9
3
fall
x
(1) With x = 0 or 1.
Fig 28. Capture mode
14
7
aaa-018997
9.10.1.3 Counter/timer mode
The counter/timer can be used to generate interrupts, based on the timers or event
counting, for software to use. When used as a timer the clock source is taken from the
system clock, prescaled if required. The timer period is programmed into the fall register
and the Fall register match interrupt enabled. The timer is started as either a single-shot
or a repeating timer, and generates an interrupt when the counter reaches the Fall register
value.
When used to count external events on TIM0CK_GT, the clock source is selected from the
input pin and the number of events programmed into the Fall register. The Fall register
match interrupt is enabled and the counter started, usually in single shot mode. An
interrupt is generated when the programmed number of transitions is seen on the input
pin. The transitions counted can configure to be rising, falling or both rising and falling
edges. This feature is available only for Timer0.
Edges on the event signal must be at least 100 ns apart, that is pulses must be wider than
100 ns.
9.10.1.4 Delta-sigma mode
A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be
implemented with up to 17-bit resolution. This requires that a resistor-capacitor network is
placed between the output DIO pin and digital ground. A stream of pulses with digital
voltage levels is generated which is integrated by the RC network to give an analog
voltage. A conversion time is defined in terms of a number of clock cycles. The width of
the pulses generated is the period of a clock cycle. The number of pulses output in the
cycle, together with the integrator RC values, will determine the resulting analog voltage.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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