JN517X Datasheet, PDF (24/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
The supply voltage detect is enabled by default from power-up and can extend the reset
during power-up. This will keep the CPU in reset until the voltage exceeds the SVM
threshold voltage. The threshold voltage is configurable to 1.95 V, 2.0 V, 2.1 V, 2.2 V,
2.3 V, 2.4 V, 2.7 V and 3.0 V and is controllable by software. From power-up, the threshold
is set by a setting within the Flash and the default chip configuration is for the 2.0 V
threshold. It is expected that the threshold is set to the minimum needed by the system.
See Figure 47 for more details on BOR and SVM characteristics.
9.5.5 Watchdog timer
A watchdog timer is provided to guard against software lockups. It operates by counting
cycles of the high-speed RC system clock. A pre-scaler is provided to allow the expiry
period to be set between typically 8 ms and 16.4 s (dependent on high-speed RC
accuracy: +30 %, 15 %). Failure to restart the watchdog timer within the pre-configured
timer period will cause a chip reset to be performed. A status bit is set if the watchdog was
triggered so that the software can differentiate watchdog initiated resets from other resets,
and can perform any required recovery once it restarts. Optionally, the watchdog can
cause an exception rather than a reset, this preserves the state of the memory and is
useful for debugging.
After power-up, reset, start from deep sleep or start from sleep, the watchdog is always
enabled with the largest time-out period and will commence counting as if it had just been
restarted. Under software control, the watchdog can be disabled. If it is enabled, the user
must regularly restart the watchdog timer to stop it from expiring and causing a reset. The
watchdog runs continuously, even during doze, however the watchdog does not operate
during sleep or deep sleep, or when the hardware debugger has taken control of the CPU.
It will recommence automatically if enabled once the debugger unstalls the CPU.
9.6 Nested Vector Interrupt controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late-arriving interrupts. The main features of
the interrupt controller are:
• Controls the system exceptions and peripheral interrupts
• Supports 20 vectored interrupts
• 16 programmable interrupt priority levels
Interrupts can be used to wake the JN517x from sleep or deep sleep. The peripherals,
baseband controller, security coprocessor and NVIC are powered down during sleep or
deep sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and
analog comparator interrupts remain powered to bring the JN517x out of sleep.
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register (VTOR) contained in the Cortex-M3. The NVIC is described in detail in the
Cortex-M3 Technical Reference Manual that can be found on official ARM website.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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