JN517X Datasheet, PDF (56/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
7
SCL
8
Ack
STSD
interrupt
1
TX/TXS_FIFO not flushed
≥ stretch clock
2
8
Ack
flush TX/TXS_FIFO
clear int and fill
TX/TXS_FIFO
1
SDA
Master transmits
RESTART
NoAck
from Master
(slave aborts transfer)
Master sends
slave address + read bit
Fig 42. Example of use of the STSD interrupt (RESTART case)
Slave transmits
Slave acknowledges
and takes over the SDA line
aaa-015462
9.14.5 Particular cases on I²C-bus
9.14.5.1
I²C-bus error
In a protocol violation on the I²C-bus, i.e., an unexpected START or STOP in the middle of
a transfer, the I²C-bus Error interrupt is set. On detection of an unexpected stop condition,
the device goes to the IDLE state and releases SDA and SCL. In case of an unexpected
restart condition, the device releases SDA and SCL checks whether it is addressed as a
slave.
9.14.5.2 Arbitration lost
When arbitration loss occurs, the Transmitter Arbitration Failure interrupt (TAF: bit 1 of the
Int_Status register) is automatically set. This means that the data bytes stored in the
TX_FIFO and the RX_FIFO are not valid, since the transfer was interrupted. The
TX_FIFO must be flushed (I2C_Control register bit 3) before clearing the interrupt. On
detection of an arbitration loss, the master will immediately release the I²C-bus (IDLE
state).
Likewise, the data in the RX_FIFO is invalid and must be read by the system to empty the
RX_FIFO. Until this is done, access to the RX_FIFO from I²C-bus is blocked by clock
stretching as described in Section 9.14.3.
9.14.5.3 NAck from slave receiver
If a master transmitter receives a NAck from the addressed slave, the master will
automatically generate a STOP and break off the transfer. The user must manually flush
the TX_FIFO before clearing the interrupt.
Software can add data to the TX_FIFO, since there is no blocking from the system bus,
however this data must be flushed again later to start normal master operation again.
9.15 Random number generator
A random number generator is provided which creates a 16-bit random number each time
it is invoked. Consecutive calls can be made to build up any length of random number.
Each call takes approximately 0.25 ms to complete. Alternatively, continuous generation
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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