JN517X Datasheet, PDF (22/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
150 s) to allow the Flash and EEPROM bandgaps to stabilize and allow their
initialization, including reading the user SVM threshold from the Flash. This is applied to
the SVM, and after a brief pause (approximately 2.5 s) the SVM is checked again. If the
supply is above the new SVM threshold, the CPU and peripheral logic is released from
reset and the CPU starts to run code beginning at the reset vector. This runs the
bootloader code contained within the Flash, which looks for a valid application to run, first
from the internal Flash and then from any connected external serial memory over the
SPI-bus master interface. Once found, required variables are initialized in RAM before the
application is called at its AppColdStart entry point. For more details on the bootloader,
refer to Application Note Boot loader Operation JN-AN-1003 on the Wireless Connectivity
area of the NXP web site Ref. 2.
The JN517x has 5 sources of reset:
• Internal Power-On Reset/Brown-Out Reset (BOR)
• External reset
• Software reset
• Watchdog timer
• Supply voltage detect
Remark: When the device exits a reset condition, device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure operation. If these conditions are not
met, then the device must be held in reset until the operating conditions are met
(see Section 14.3.1).
9.5.1 Internal Power-On Reset/Brown-out Reset (BOR)
For most applications, the Internal POR is capable of generating the required reset signal.
When power is applied to the device, the power-on reset circuit monitors the rise of the
V_DD (V_DDA and V_DDD) supply. When the V_DD reaches the specified threshold, the reset
signal is generated. This signal is held internally until the power supply and oscillator
stabilization time has elapsed, when the internal reset signal is then removed and the
CPU is allowed to run.
The BOR circuit has the ability to reject spikes on the V_DD rail to avoid false triggering of
the reset module. Typically for a negative going square pulse of duration 1 s, the voltage
must fall to 1.2 V before a reset is generated. Similarly for a triangular wave pulse of 10 s
width, the voltage must fall to 1.3 V before causing a reset. The exact characteristics are
complex and these are only examples. See Figure 47 for more details on BOR and SVM
characteristics.
V_DD
internal RESET
Fig 12. Internal Power-On Reset
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
aaa-017251
© NXP Semiconductors N.V. 2016. All rights reserved.
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