JN517X Datasheet, PDF (35/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
Table 4. SPI-bus master I/O
Signal
DIO assignment
Standard pins
SPISEL0
DIO6
SPISEL1
DIO15
SPISEL2
-
SPICLK
DO0
SPIMISO
DO1
SPIMOSI
DIO7
Alternative pins
DIO0, DIO17
-
DIO7
DIO11
DIO18
DIO15
The interface can transfer from 1 bit to 32 bits without software intervention and can keep
the slave select lines asserted between transfers when required, to enable longer
transfers to be performed.
When the device reset is active, all the SPI-bus master pins are configured as inputs with
their pull-up resistors active. The pins stay in this state until the SPI-bus master block is
enabled, or the pins are configured for some other use.
SLAVE 0
FLASH/ _SS
EEPROM
MEMORY
SLAVE 1
USER SS
DEFINED
SLAVE 2
USER SS
DEFINED
SI C SO
SI C SO
SI C SO
JN517x
SPIMOSI
SPICLK
SPIMISO
aaa-021460
Fig 24. Typical JN517x SPI-bus peripheral connection
The data transfer rate on the SPI-bus is determined by the SPICLK signal. The JN517x
supports transfers at data rates from 16 MHz to 125 kHz selected by a clock divider. Both
SPICLK clock phase and polarity are configurable. The clock phase determines which
edge of SPICLK is used by the JN517x to present new data on the SPIMOSI line; the
opposite edge will be used to read data from the SPIMISO line. The interface should be
configured appropriately for the SPI-bus slave being accessed.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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