MC68HC08AS32 Datasheet, PDF (97/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Clock Generator Module (CGM)
Functional Description
Table 8-1. CGM I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$001C
PLL Control Register ^Read:
(PCTL) _Write:
PLLIE
PLLF
R
PLLON
BCS
1
R
1
R
1
R
1
R
$001D
PLL Bandwidth Control Register ^Read:
(PBWC) _Write:
AUTO
LOCK
R
ACQ
XLD
0
R
0
R
0
R
0
R
$001E
PLL Programming Register ^Read:
(PPG) _Write:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
R = Reserved
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually. While reading this section, refer
to 21.9 CGM Operating Conditions for operating frequencies.
8.4.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. (For maximum immunity guidelines on
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Clock Generator Module (CGM)
Advance Information
97