MC68HC08AS32 Datasheet, PDF (114/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Clock Generator Module (CGM)
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Special Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
8.8.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
8.8.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock (CGMVCLK)
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock
(CGMXCLK) divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
Advance Information
114
Clock Generator Module (CGM)
MC68HC08AS32 — Rev. 3.0
MOTOROLA