MC68HC08AS32 Datasheet, PDF (163/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Monitor ROM (MON)
Functional Description
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Table 12-2 is a summary of the differences between user mode and
monitor mode.
Table 12-2. Mode Differences
Functions
Modes
COP
Reset Reset Break Break SWI
SWI
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
User
Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor Disabled⁽¹⁾ $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
1. If the high voltage (V_DD + V_HI) is removed from the IRQ/V_PP pin while in monitor mode, the
SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register. (See 21.5 5.0-Volt DC Electrical Characteristics
Control Timing.)
12.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3.)
The data transmit and receive rate can be anywhere from 4800 baud to
28.8 kBaud. Transmit and receive baud rates must be identical.
NEXT
START
START
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
Figure 12-2. Monitor Data Format
$A5
BREAK
START
BIT
BIT 0
START
BIT
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 12-3. Sample Monitor Waveforms
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Monitor ROM (MON)
Advance Information
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