MC68HC08AS32 Datasheet, PDF (119/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
8.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations in this subsection. These equations yield nominal values
under the following conditions:
• Correct selection of filter capacitor, C_F (See 8.10.3 Choosing a
Filter Capacitor.)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. (See
8.4.2.2 Acquisition and Tracking Modes.)
tACQ
=



V--f--R-D---D-D----V-A---_{}


K-----A---8-C-----Q---^
tAL
=



V--f--R-D---D-D----V-A---_{}


K-----T--4--R----K---^
tLock = tACQ + tAL
NOTE: There is an inverse proportionality between the lock time and the
reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See 8.4.2.3
Automatic and Manual PLL Bandwidth Modes.) A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆_TRK, before exiting acquisition mode.
Additionally, a certain number of clock cycles, n_TRK, is required to
ascertain that the PLL is within the lock mode entry tolerance, ∆_Lock.
Therefore, the acquisition time, t_ACQ, is an integer multiple of n_ACQ/f_RDV,
and the acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV.
MC68HC08AS32 — Rev. 3.0
Advance Information
MOTOROLA
Clock Generator Module (CGM)
119