MC68HC08AS32 Datasheet, PDF (149/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Low-Voltage Inhibit (LVI)
LVI Interrupts
10.6 LVI Interrupts
The LVI module does not generate interrupt requests.
10.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power standby
modes.
10.7.1 Wait Mode
With the LVIPWR bit in the MOR register programmed to logic 1, the LVI
module is active after a WAIT instruction.
With the LVIRST bit in the MOR register programmed to logic 1, the LVI
module can generate a reset and bring the MCU out of wait mode.
10.7.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip must bypass the digital filter to generate a reset and bring the MCU
out of stop.
With the LVIPWR bit in the MOR register programmed to logic 1 and the
LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP
instruction.
NOTE: If the LVIPWR bit is at logic 1, the LVISTOP bit must be at logic 0 to meet
the minimum stop mode I_DD specification.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Low-Voltage Inhibit (LVI)
Advance Information
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