MC68HC08AS32 Datasheet, PDF (112/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Clock Generator Module (CGM)
8.6.3 PLL Programming Register
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $001E
Bit 7
6
5
4
3
2
1
Read:
MUL7
Write:
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
Reset: 0
1
1
0
0
1
1
Figure 8-5. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 8.4.2 Phase-Locked Loop
Circuit (PLL).) A value of $0 in the multiplier select bits configures the
modulo feedback divider the same as a value of $1. Reset initializes
these bits to $6 to give a default multiply value of 6.
Table 8-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
Advance Information
112
Clock Generator Module (CGM)
MC68HC08AS32 — Rev. 3.0
MOTOROLA