MC68HC08AS32 Datasheet, PDF (173/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Computer Operating Properly (COP)
COP Control Register
13.4.7 COPS (COP Short Timeout)
The COPS bit selects the state of the COP short timeout bit (COPS) in
the MOR register ($001F). Timeout periods can be (2¹⁸ –2⁴⁾ or (2¹³ –2⁴⁾
CGMXCLK cycles. (See 5.4 Mask Option Register.)
13.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low Byte of Reset Vector
Write:
Clear COP Counter
Reset:
Unaffected by Reset
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when V_DD + V_HI (see 21.5
5.0-Volt DC Electrical Characteristics Control Timing) is present on
the IRQ pin or on the RST pin.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Computer Operating Properly (COP)
Advance Information
173