MC68HC08AS32 Datasheet, PDF (126/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

System Integration Module (SIM)
9.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 9.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can
be programmed to be active in wait mode. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode.
9.4 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
Each of these resets produces the vector $FFFE–FFFF ($FEFE–FEFF
in monitor mode) and asserts the internal reset signal (IRST). IRST
causes all registers to be returned to their default values and all modules
to be returned to their reset states.
An internal reset clears the SIM counter (see 9.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 9.8 SIM Registers.)
Advance Information
126
System Integration Module (SIM)
MC68HC08AS32 — Rev. 3.0
MOTOROLA