MC68HC08AS32 Datasheet, PDF (107/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Clock Generator Module (CGM)
CGM Registers
8.6 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) (See 8.6.1 PLL Control Register.)
• PLL bandwidth control register (PBWC) (See 8.6.2 PLL
Bandwidth Control Register.)
• PLL programming register (PPG) (See 8.6.3 PLL Programming
Register.)
Table 8-2 is a summary of the CGM registers.
Table 8-2. CGM I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$001C
PLL Control Register ^Read:
(PCTL) _Write:
PLLIE
PLLF
R
PLLON
BCS
1
R
1
R
1
R
1
R
$001D
PLL Bandwidth Control Register ^Read:
(PBWC) _Write:
AUTO
LOCK
R
ACQ
XLD
0
R
0
R
0
R
0
R
$001E
PLL Programming Register ^Read:
(PPG) _Write:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Clock Generator Module (CGM)
Advance Information
107