MC68HC08AS32 Datasheet, PDF (154/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Break Module (Break)
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC–$FFFD
($FEFC–$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_DD + V_HI is present
on the RST pin. For V_HI, see 21.5 5.0-Volt DC Electrical
Characteristics Control Timing.
11.5 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
Advance Information
154
Break Module (Break)
MC68HC08AS32 — Rev. 3.0
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