MC68HC08AS32 Datasheet, PDF (265/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Serial Communications Interface (SCI)
I/O Registers
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. (See Figure 17-9.) Reset clears
PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
17.9.4 SCI Status Register 1
SCI status register 1 contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
Read: SCTE
TC
SCRF IDLE
OR
NF
FE
PE
Write: R
R
R
R
R
R
R
R
Reset: 1
1
0
0
0
0
0
0
R = Reserved
Figure 17-9. SCI Status Register 1 (SCS1)
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Serial Communications Interface (SCI)
Advance Information
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