MC68HC08AS32 Datasheet, PDF (348/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
20.6.5 State Machine
All of the functions associated with performing the protocol are executed
or controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
20.6.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but can
receive messages in 4X mode, if the RX4X bit is set in BCR2 register. If
the RX4X bit is not set in the BCR2 register, any 4X message on the
J1850 bus is treated as noise by the BDLC and is ignored.
20.6.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All of the other features of
the frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
20.6.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR register until the message is complete.
The programmer should wait until the TDRE flag (see 20.7.4 BDLC
State Vector Register) is set prior to writing a new byte of data into the
BDR register. The BDLC does not contain any predefined maximum
J1850 message length requirement.
Advance Information
348
Byte Data Link Controller-Digital (BDLC-D)
MC68HC08AS32 — Rev. 3.0
MOTOROLA