MC68HC08AS32 Datasheet, PDF (355/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked and the status bits will be held in their reset state. If
this bit is set while the BDLC is receiving a message, the rest
of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
The nominal BDLC operating frequency (f_BDLC) must always be
1.048576 MHz or 1 MHz for J1850 bus communications to take place.
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to adjust symbol timing automatically.
1 = Binary frequency (1.048576 MHz) selected for f_BDLC
0 = Integer frequency (1 MHz) selected for f_BDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (f_BDLC)
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become
read-only bits.
The nominal frequency of f_BDLC must always be 1.048576 MHz or 1.0
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per Table 20-4.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
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