MC68HC08AS32 Datasheet, PDF (198/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Input/Output (I/O) Ports
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See 18.14.1 SPI Control Register.)
SS — Slave Select Bit
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See 18.13.4 SS (Slave Select).) When the SPI is enabled as a
slave, the DDRE4 bit in data direction register E (DDRE) has no effect
on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-6.)
TCH[1:0] — Timer Channel I/O Bits
The PTE3/TCH1–PTE2/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTE3/TCH1–PTE2/TCH0 pins are timer channel I/O pins
or general-purpose I/O pins. (See 16.9.4 TIM Channel Status and
Control Registers.)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-6.)
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See 17.9.1
SCI Control Register 1.)
Advance Information
198
Input/Output (I/O) Ports
MC68HC08AS32 — Rev. 3.0
MOTOROLA