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MC68HC08AS32 Datasheet, PDF (335/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
receiving a message in 4X mode, the BDLC detects a BREAK
symbol, it treats the BREAK as a reception error, sets the invalid
symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK
symbol is received and the IFS time has elapsed, the programmer
must resend the transmission byte using highest priority.
NOTE: The J1850 protocol BREAK symbol is not related to the HC08 break
module (See Section 11. Break Module (Break).)
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for instance, ≥ 300 µs). Any node sensing
an idle bus condition can begin transmission immediately.
20.5.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
(tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
(EOF), and inter-frame separation (IFS) symbols always will be encoded
at an assigned level and length. See Figure 20-6.
Each message will begin with an SOF symbol an active symbol and,
therefore, each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values
at a 10.4 kbps bit rate.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
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