MC68HC08AS32 Datasheet, PDF (171/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Computer Operating Properly (COP)
Functional Description
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. COP timeouts are determined
strictly by the CGM crystal oscillator clock signal (CGMXCLK), not the
CGMOUT signal (see Figure 8-1. CGM Block Diagram).
If not cleared by software, the COP counter overflows and generates an
asynchronous reset after (2¹³ – 2⁴) or (2¹⁸ – 2⁴) CGMXCLK cycles,
depending upon COPS bit in the MOR register ($001F) (See Section 5.
Mask Options.) With a 4.9152-MHz crystal and the COPS bit in the
MOR register ($001F) set to a logic 1, the COP timeout period is
approximately 53.3 ms. Writing any value to location $FFFF before
overflow occurs clears the COP counter, clears bits 12 through 4 of the
SIM counter, and prevents reset. A CPU interrupt routine can be used to
clear the COP.
NOTE:
The COP should be serviced as soon as possible out of reset and before
entering or after exiting stop mode to guarantee the maximum selected
amount of time before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see 9.8.2 SIM Reset
Status Register).
NOTE:
While the microcontroller is in monitor mode, the COP module is
disabled if the RST pin or the IRQ pin is held at V_DD + V_HI (see 21.5
5.0-Volt DC Electrical Characteristics Control Timing). During a
break state, V_DD + V_HI on the RST pin disables the COP module.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly. The one exception to this is wait mode (see 13.8.1 Wait
Mode).
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Computer Operating Properly (COP)
Advance Information
171