MC68HC08AS32 Datasheet, PDF (327/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
Functional Description
20.4.1.1 Power Off Mode
This mode is entered from reset mode whenever the BDLC supply
voltage, V_DD, drops below its minimum specified value for the BDLC to
guarantee operation. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In this mode, the
pin input and output specifications are not guaranteed.
20.4.1.2 Reset Mode
This mode is entered from the power off mode whenever the BDLC
supply voltage, V_DD, rises above its minimum specified value
(V_DD –10%) and some MCU reset source is asserted. The internal MCU
reset must be asserted while powering up the BDLC or an unknown
state will be entered and correct operation cannot be guaranteed. Reset
mode is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, and reset
pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative; V_DD
is supplied to the internal circuits which are held in their reset state; and
the internal BDLC system clock is running. Registers will assume their
reset condition. Outputs are held in their programmed reset state.
Therefore, inputs and network activity are ignored.
20.4.1.3 Run Mode
This mode is entered from the reset mode after all MCU reset sources
are no longer asserted. Run mode is entered from the BDLC wait mode
whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network
activity is sensed, although messages will not be received properly until
the clocks have stabilized and the CPU is in run mode also.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
327