MC68HC08AS32 Datasheet, PDF (356/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
Table 20-4. BDLC Rate Selection
f_XCLK Frequency
R1
1.049 MHz
0
2.097 MHz
0
4.194 MHz
1
8.389 MHz
1
1.000 MHz
0
2.000 MHz
0
4.000 MHz
1
8.000 MHz
1
R0
Division
0
1
1
2
0
4
1
8
0
1
1
2
0
4
1
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See 20.7.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode.
See 20.8.2 Stop Mode and 20.8.1 Wait Mode for more details on its
use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
Advance Information
356
Byte Data Link Controller-Digital (BDLC-D)
MC68HC08AS32 — Rev. 3.0
MOTOROLA