MC68HC08AS32 Datasheet, PDF (147/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Low-Voltage Inhibit (LVI)
Functional Description
V_DD
LOW V_DD
DETECTOR
LVIPWR
FROM CONFIG
CPU CLOCK
V_DD > V_LVIR = 0
V_DD < V_LVIF = 1
V_DD
DIGITAL FILTER
FROM CONFIG
LVIRST
ANLGTRIP
STOP MODE
FILTER BYPASS
LVISTOP
FROM CONFIG
LVIOUT
Figure 10-1. LVI Module Block Diagram
Addr.
$FE0F
Table 10-1. LVI I/O Register Summary
Register Name
Bit 7 6
5
4
3
LVI Status Register (LVISR) LVIOUT R
R
R
R
LVI RESET
2
1 Bit 0
R
R
R
R = Reserved
10.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_LVIF level,
software can monitor V_DD by polling the LVIOUT bit. In the MOR
register, the LVIPWR bit must be at logic1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
10.4.2 Forced Reset Operation
In applications that require V_DD to remain above the V_LVIF level, enabling
LVI resets allows the LVI module to reset the MCU when V_DD falls to the
V_LVIF level and remains at or below that level for nine or more
consecutive CPU cycles. In the MOR register, the LVIPWR and LVIRST
bits must be at logic 1 to enable the LVI module and to enable LVI resets.
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Low-Voltage Inhibit (LVI)
Advance Information
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