MC68HC08AS32 Datasheet, PDF (254/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Serial Communications Interface (SCI)
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTE1/RxD pin. The idle
line interrupt enable bit, ILIE (SCC2), enables the IDLE bit to
generate CPU interrupt requests.
17.5.1 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
• Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE (SCC3), enables OR to generate SCI
error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE (SCC3), enables
NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE (SCC3), enables FE to generate SCI
error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE (SCC3), enables PE to generate SCI error CPU
interrupt requests.
Advance Information
254
Serial Communications Interface (SCI)
MC68HC08AS32 — Rev. 3.0
MOTOROLA