MC68HC08AS32 Datasheet, PDF (365/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Table 20-6. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
Interrupt Source
Priority
$00 0 0 0 0
No Interrupts Pending
0 (Lowest)
$04 0 0 0 1
Received EOF
1
$08 0 0 1 0
Received IFR Byte (RXIFR)
2
$0C 0 0 1 1 BDLC Rx Data Register Full (RDRF)
3
$10 0 1 0 0 BDLC Tx Data Register Empty (TDRE)
4
$14 0 1 0 1
Loss of Arbitration
5
$18 0 1 1 0 Cyclical Redundancy Check (CRC) Error
6
$1C 0 1 1 1
Symbol Invalid or Out of Range
7
$20 1 0 0 0
Wakeup
8 (Highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the
BDLC data register needs servicing (RDRF, RXIFR, or TDRE
conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can
either be cleared by a read of the BSVR followed by a write to the BDLC
BDR or by setting the TEOD bit in BCR2.
Upon receiving a BDLC interrupt, the user can read the value within the
BSVR, transferring it to the CPU’s index register. The value can then be
used to index into a jump table, with entries four bytes apart, to quickly
enter the appropriate service routine. For example:
Service
*
*
JMPTAB
*
LDX BSVR
JMP JMPTAB,X
JMP SERVE0
NOP
JMP SERVE1
NOP
JMP SERVE2
NOP
JMP SERVE8
END
Fetch State Vector Number
Enter service routine,
(must end in RTI)
Service condition #0
Service condition #1
Service condition #2
Service condition #8
MC68HC08AS32 — Rev. 3.0
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
Advance Information
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