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MC68HC08AS32 Datasheet, PDF (374/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)
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Electrical Specifications
21.5 5.0-Volt DC Electrical Characteristics Control Timing
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output High Voltage
(ILoad = –2.0 mA) All Ports, RESET
Output Low Voltage
(ILoad = 1.6 mA) All Ports, RESET
Input High Voltage
All Ports, IRQs, RESET, OSC1
VOH
VDD –0.8
—
—
V
VOL
—
—
0.4
V
VIH
0.7 x VDD —
VDD
V
Input Low Voltage
All Ports, IRQs, RESET, OSC1
VIL
VSS
— 0.3 x VDD
V
VDD + VDDA/VDDAREF Supply Current
Run(3)
Wait(4)
Stop(5)
25 °C
–40 °C to +105 °C
25 °C with LVI Enabled
–40 °C to +105 °C with LVI Enabled
—
—
30
mA
—
—
15
mA
IDD
—
—
5
µA
—
—
50
µA
—
—
400
µA
—
—
500
µA
I/O Ports Hi-Z Leakage Current
IL
—
—
±1
µA
Input Current
IIN
—
—
±1
µA
Capacitance
Ports (As Input or Output)
COUT
CIN
—
—
—
—
12
8
pF
Low-Voltage Reset Inhibit
VLVF
3.7
4.1
4.45
V
Low-Voltage Reset Inhibit/Recover Hysteresis
POR ReArm Voltage(6)
POR Reset Voltage(7)
POR Rise Time Ramp Rate(8)
High COP Disable Voltage(9)
HLVI
VPOR
VPORRST
RPOR
VHI
50
0
0
0.02
VDD
150
—
mV
—
200
mV
—
800
mV
—
—
V/ms
VDD + 2
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dcloads. Less
than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. See 13.9 COP Module During Break Interrupts.
Advance Information
374
Electrical Specifications
MC68HC08AS32 — Rev. 3.0
MOTOROLA
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