MC68HC08AS32 Datasheet, PDF (23/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

List of Figures
Figure
Title
Page
19-3
19-4
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .318
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . .318
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . .326
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . .330
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . .332
J1850 VPW Symbols with Nominal Symbol Times . . . . . .336
J1850 VPW Received Passive Symbol Times . . . . . . . . . .339
J1850 VPW Received Passive
EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . .340
J1850 VPW Received Active Symbol Times . . . . . . . . . . .341
J1850 VPW Received BREAK Symbol Times . . . . . . . . . .342
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . .343
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . .346
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
BDLC Analog and Roundtrip Delay Register (BARD) . . . .353
BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . .354
BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . .357
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . .360
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . .364
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . .366
21-1
21-2
21-3
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
BDLC Variable Pulse Width Modulation (VPW)
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
MC68HC08AS32 — Rev. 3.0
MOTOROLA
List of Figures
Advance Information
23