MC68HC08AS32 Datasheet, PDF (340/394 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Byte Data Link Controller-Digital (BDLC-D)
280 µs
300 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 20-8. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbol
In Figure 20-8(1), if the passive-to-active received transition
beginning the SOF symbol of the next message occurs between a
and b, the current symbol will be considered a valid end-of-frame
(EOF) symbol.
See Figure 20-8(2). If the passive-to-active received transition
beginning the SOF symbol of the next message occurs between c
and d, the current symbol will be considered a valid EOF symbol
followed by a valid inter-frame separation symbol (IFS). All nodes
must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node
waiting to transmit detects a passive-to-active transition once a valid
EOF has been detected, it should immediately begin transmission,
initiating the arbitration process.
Idle Bus
In Figure 20-8(2), if the passive-to-active received transition
beginning the start-of-frame (SOF) symbol of the next message does
not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
Advance Information
340
Byte Data Link Controller-Digital (BDLC-D)
MC68HC08AS32 — Rev. 3.0
MOTOROLA